1. Field of the Invention
This invention relates to a wiring placement method and to a semiconductor integrated circuit device utilizing that wiring placement method.
2. Description of Related Art
Reducing timing delays and current consumption is a major problem when designing semiconductor integrated circuit devices. As semiconductor integrated circuit devices achieve higher performance, greater attention is being focused on effects that inter-wiring capacitance exerts on timing delays and current consumption. The smaller the inter-wiring capacitance, the more that timing delays and power consumption are reduced. Minimizing this inter-wiring capacitance by optimal wiring placement in semiconductor integrated circuit devices is therefore essential.
Wiring placement in semiconductor integrated circuit devices with multiple layer wiring structures in the conventional art is described next. FIG. 10 shows an example of wiring connections between the start point group and end point group in a region on the semiconductor integrated circuit device. The procedure for the wiring placement in FIG. 10 is described next.
FIG. 7 shows the relative positions of the start point group and the end point group. A start point group made up of the eight start points A through H; and an end point group made up of eight end points A′ through H′ are respectively arrayed in straight lines. The straight line formed by the start point group and the straight line formed by the end point group intersect each other. Though the example described here utilizes eight sets with a start point and an end point as one set, the following discussion is not limited to eight sets.
FIG. 8 is a drawing showing the horizontal wiring length (namely the direction along the end points). As seen in FIG. 8, eight wires of different lengths in parallel with the end point group are needed when each individual start point is connected to an individual end point in a one-to-one relation formed by a wiring group in parallel with the end point group and a wiring group in parallel with the start point group.
FIG. 9 shows the progression of mask data in the wiring placement as the wiring process of the conventional art proceeds. FIG. 9 shows the wiring along the horizontal direction for the case where making the length of each wire connecting the start point and the end point equal.
FIG. 10 is a drawing showing the progression of mask data in the wiring placement during the wiring process of the conventional art. Here, the wiring group in the vertical direction (in other words, along the start point group direction) connects the end point group and wiring group of FIG. 9 on different layers than the wiring groups in FIG. 9. Contacts (not shown in drawing) are placed at the sections connecting the horizontal wiring group and the vertical wiring group.
The start points and the end points are connected by wiring spanning two layers. All wiring connecting the start points and the end points can be placed on two layers by using a different layer for each wiring direction. Therefore, the wiring placement shown in FIG. 10 is mostly used. Moreover, even though the wiring lengths on each layer are different, the wires joining the start points and end points are a fixed length. However, the wire placement shown in FIG. 10 has the problem that the side wall capacitance increases as the device process rule shrinks and the gaps between adjacent wiring become narrower.
FIG. 11 shows the parallel wiring disclosed in the patent document 1 for resolving the problems of the conventional art. The differential transmission line paths (L1a, L1b), (L2a, L2b), (L3a, L3b) are placed on the Si (silicon) substrate 20 within the LSI. Each of the signal lines for the differential transmission line paths (for example L1a and L1b) is formed at positions diagonally opposite the horizontal direction (standard direction). An Inter-Layer Dielectric, ILD10 is formed between the wiring of each differential transmission line paths.
The signal lines L1a, L1b, L2a, L2b, L3a, L3b, are all made from metallic material such as aluminum. The ILD10 is made from SiO2, etc.
The parallel wirings disclosed in patent document 1 are multiple differential line paths formed in parallel with each other in the standard direction. Each of these differential line paths includes two lines approximately in parallel. Here, a unique feature is that the wiring layers of these two lines can be changed. The side wall capacitance can in other words be suppressed by extending the distance between adjacent lines.
Patent document 2 discloses a method for minimizing signal delay caused by parasitic CR among wiring when multiple signal wires are in parallel with each other, by adjusting the gap between adjacent signal lines or signal line widths.    [Patent document 1] Japanese Unexamined Patent Application Publication No. 2005-101587    [Patent document 2] Japanese Unexamined Patent Application Publication No. Hei06(2004)-302694